1. Field of the Invention
This invention relates to solid state photo-sensors and imagers and, more particularly, to charge-to-voltage conversion structures of charge coupled devices.
2. Description of the Prior Art
Solid state photo-sensors and imagers operate by converting incident optical energy into charge packets that are spatially correlated to the incident optical image. In order to reconstruct and/or store the image in another medium, the photo-charge is typically converted to voltage. This is usually accomplished by transferring the photo-charge onto an integrated capacitor. The charge is thus converted to a voltage by the relationship, V=Q/C; where V is voltage, Q is charge, and C is capacitance.
In an application where light levels are low, (such as copiers), it is desirable to make this capacitance as small as possible so that the sensitivity, which is defined as dV/dQ, is sufficiently large to provide an adequate output voltage swing with these lower illumination levels. To this end, the capacitor is typically realized by a floating diffusion. This is typically achieved by employing a floating diffusion to create the capacitor and realize the necessary voltage swing. The floating diffusion is typically formed by a shallow implant and contacted via metalization that connects the floating diffusion to the gate of a MOS transistor used as an amplifier. The capacitance of the floating diffusion node is increased by the parasitic capacitance that is associated with the metalization interconnect and the MOS transistor. Therefore, in order to keep the total capacitance resulting at the floating diffusion node small, it is desirable to minimize this parasitic capacitance as well as to reduce the junction capacitance of the floating diffusion region.
One method to minimize the parasitic capacitance, was presented by K. Miwada, et. al., "A 100 MHz Data-Rate, 5000-Element CCD Linear Image Sensor with Reset Pulse Level Adjustment Circuit", IEEE Int. Solid-St. Circ. Conf. Tech. Digest, pp. 168-169, 275, 1992. In this approach a "buried contact" is created that eliminates the need for any metal interconnect between the floating diffusion and the gate of the MOS amplifier. This approach however, has some disadvantages. First it requires the addition of an extra mask and lithography sequence to the baseline image sensor process. It also requires either direct contact of the gate oxide with photoresist, or additional process steps to prevent direct contact. As a result, the yield and cost of the device is adversely affected.
An improved low capacitance floating diffusion structure was devised and disclosed by R. M. Guidash and A. S. Ciccarelli in U.S. application Ser. No. 08/188,500 filed Jan. 26, 1994 and entitled "A Low Capacitance Floating Diffusion Structure for a Solid State Image Sensor and Method for Producing Such a Structure", which is commonly assigned with the present invention. In this structure the contact area with the floating diffusion is formed through an opening in a gate electrode. This structure overcomes the disadvantages cited in the prior art, but still places some limitations on the reduction in the floating diffusion area contained between the reset gate and output gate. The junction capacitance of the floating diffusion structure is directly proportional to this area. In order to further reduce the floating diffusion junction capacitance it is desirable to make the floating diffusion region between the reset gate and output gate smaller.
As can be seen by the foregoing description, there remains a need within the prior art for a floating diffusion structure that has reduced capacitance from existing structures.